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Spiking Neural Networks (SNN)
Artificial neural networks that communicate through discrete spikes rather than continuous values, thus more faithfully mimicking the operation of biological neurons for more energy-efficient information processing.
Address Event Representation (AER)
Asynchronous communication protocol where each event (spike) is transmitted with the address of the emitting neuron, optimizing bandwidth and energy consumption in distributed neuromorphic systems.
Memristor-Based Computing
Computing architecture using memristors as physical synaptic elements, enabling direct implementation of variable synaptic weights and local learning rules in neuromorphic hardware.
Neuromorphic Processors
Specialized processing units designed to implement neuron and synapse models directly in silicon, offering massively parallel performance and superior energy efficiency for AI workloads.
Silicon Neurons
Electronic circuits that reproduce the dynamic characteristics of biological neurons, including temporal integration, activation thresholds, and refractory periods, forming the basic elements of neuromorphic architectures.
Hierarchical Temporal Memory (HTM)
Biomimetic algorithm inspired by the neocortex, using distributed sparse memories and temporal predictions for sequence learning and pattern recognition in data streams.
Local Learning Rules
Learning rules where synaptic weight updates depend only on local information available at each synapse, eliminating the need for global backpropagation and enabling real-time learning on neuromorphic hardware.
On-Chip Learning
Ability of neuromorphic systems to adapt their parameters directly on the chip without external intervention, allowing continuous and autonomous adaptation to changes in the environment or input data.
Asynchronous Computing
Computing approach where operations are not synchronized by a global clock but occur independently when relevant events happen, reducing latency and power consumption in neuromorphic architectures.
Crossbar Architecture
Hardware structure organized in a grid where rows represent presynaptic neurons and columns represent postsynaptic neurons, with synaptic devices at intersections, allowing dense and parallel implementation of neural connections.
Time-to-First-Spike Coding
Neural coding strategy where information is represented by the arrival time of the first spike after a stimulus, offering fast decision latency and high energy efficiency in neuromorphic systems.
Neuromorphic Sensing
Sensors that directly transform physical signals into asynchronous events similar to neural spikes, preprocessing data at the hardware level to reduce the amount of information to transmit and process.
Hardware-in-the-Loop Simulation
Testing and development methodology where physical neuromorphic components are integrated into software simulations, enabling accelerated validation of algorithms and architectures before full deployment.
Rate Coding vs Temporal Coding
Two neural coding paradigms where the first represents information by spike frequency and the second by their precise timing, modern neuromorphic systems can exploit both approaches in a hybrid manner for optimal processing.