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RRAM
Resistive random-access memory based on memristor properties to store information by modifying the resistance of a dielectric material.
Synaptic conductance
Electrical parameter in neuromorphic circuits that simulates the connection strength between neurons by adjusting the memristor's conductance according to electrical activity.
Memristance
Fundamental property of a memristor characterizing its variable resistance that depends on the history of current that has passed through the component.
Resistive hysteresis
Phenomenon where the resistance of a memristor depends not only on the applied voltage but also on its previous state, creating a characteristic hysteresis cycle.
Conductive filament
Metallic or oxidized microstructure formed in the dielectric of a memristor by ion migration, creating a localized and reversible conduction path.
Resistance state
Quantized configuration of a memristor's resistance (HRS or LRS) representing logical states or synaptic weights in neuromorphic applications.
Electrochemical switching
Resistance change mechanism in memristors based on ion migration and redox reactions under the effect of an electric field.
Metallic dendrite
Branched metal structure formed by electrodeposition in the dielectric of a memristor, responsible for the abrupt conductance change between states.
Metal Oxide Memristor
Type of memristor using metal oxides such as HfO₂, TiO₂ or Ta₂O₅ as dielectric to achieve reliable resistive switching properties.
In-Memory Computing
Architectural approach where computations are performed directly in memory cells (memristors), eliminating the von Neumann bottleneck between processor and memory.
Non-volatile electronics
Technology based on memristors that allows maintaining logical state without continuous power supply, essential for autonomous neuromorphic systems.
Forming voltage
Initial voltage required to activate a new memristor by creating the first conductive filament, a prerequisite for its normal operation.
SET/RESET operations
Programming procedures of memristors where SET switches to low resistance state and RESET to high resistance state, simulating synaptic plasticity.